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Espressif Systems /ESP32-S2 /RTC_I2C /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SDA_FORCE_OUT)SDA_FORCE_OUT 0 (SCL_FORCE_OUT)SCL_FORCE_OUT 0 (MS_MODE)MS_MODE 0 (TRANS_START)TRANS_START 0 (TX_LSB_FIRST)TX_LSB_FIRST 0 (RX_LSB_FIRST)RX_LSB_FIRST 0 (CLK_GATE_EN)CLK_GATE_EN 0 (RESET)RESET 0 (CLK_EN)CLK_EN

Description

Transmission setting

Fields

SDA_FORCE_OUT

SDA output mode. 0: open drain. 1: push pull.
SCL_FORCE_OUT

SCL output mode. 0: open drain. 1: push pull.
MS_MODE

Set this bit to configure RTC I²C as a master.
TRANS_START

Set this bit to 1, RTC I2C starts sending data.
TX_LSB_FIRST

This bit is used to control the sending mode. 0: send data from the most significant bit. 1: send data from the least significant bit.
RX_LSB_FIRST

This bit is used to control the storage mode for received data. 0: receive data from the most significant bit. 1: receive data from the least significant bit.
CLK_GATE_EN

RTC I²C controller clock gate.
RESET

RTC I²C software reset.
CLK_EN

rtc i2c reg clk gating

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data